The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing systems and apparatuses are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also requires associated improvements in semiconductor manufacturing and processing equipment.
With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), display devices, light emitting diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed, dimensions of semiconductor integrated circuits have been reduced, and various materials and techniques have been proposed to achieve these targets and overcome obstacles during manufacturing. Due to the high-integration of semiconductor integrated circuits, the topography of a semiconductor integrated circuit on a substrate becomes rough and the surface of the substrate should be planarized/polished to facilitate deposition of subsequent layers. In order to solve this problem, chemical mechanical polishing (CMP) technology has been used. For purposes of this disclosure, the terms substrate and wafer are well known in the art and are herein used interchangeably.
Traditionally, CMP processes have been used on wafers in a face-down orientation. For ultra low K CMP processes, low force on the membrane is needed. Unfortunately, conventional CMP equipment cannot generally meet this requirement for such low force on the membrane.
Further, the downward force used in polishing may cause the wafer to flex, thereby creating dishing or a non-uniform/non-planar profile (non-U %) on the surface of the wafer. Also, such substrate flexing may induce corrosion on the wafer.
Other problems associated with traditional face-down wafer processing include the fact that in-situ wafer monitoring is not available, post CMP cleaning of the wafer cannot be performed, EPD (endpoint detection) is harder to measure and a large amount of slurry (e.g., polishing compound) is needed to spread out and wet the polishing pad.
Accordingly, what is needed is an improved CMP device that addresses the above stated issues, and a method for using such CMP device.